package jdos.hardware;

public class VGA_seq {
	static int index = 0;
	public static boolean chained = true;
	public static int full_map_mask;
	public static int full_not_map_mask;

    private static IoHandler.IO_WriteHandler write_p3c4 = new IoHandler.IO_WriteHandler() {
        public void call(/*Bitu*/int port, /*Bitu*/int val, /*Bitu*/int iolen) {
            index=(short)val;
        }
    };

    static /*Bit32u*/int[] FillTable=new int[16];
    
    static {
        for (int i=0;i<16;i++) {
            FillTable[i]=
                ((i & 1)!=0 ? 0x000000ff : 0) |
                ((i & 2)!=0 ? 0x0000ff00 : 0) |
                ((i & 4)!=0 ? 0x00ff0000 : 0) |
                ((i & 8)!=0 ? 0xff000000 : 0) ;
        }
    }
    
    private static IoHandler.IO_WriteHandler write_p3c5 = new IoHandler.IO_WriteHandler() {
        public void call(/*Bitu*/int port, /*Bitu*/int val, /*Bitu*/int iolen) {
        //	LOG_MSG("SEQ WRITE reg %X val %X",VGA.vga.seq.index),val);
            switch(index) {
            case 2:		/* Map Mask */
                full_map_mask=FillTable[val & 15];
                full_not_map_mask=~full_map_mask;
                break;
            case 4:	/* Memory Mode */

                if ((val&0x08)!=0) chained=true;//TODO unchained
                else chained=false;
                //}
                break;
            default:
                break;
            }
        }
    };

    public static void VGA_SetupSEQ() {
        IoHandler.IO_RegisterWriteHandler(0x3c4,write_p3c4,IoHandler.IO_MB);
        IoHandler.IO_RegisterWriteHandler(0x3c5,write_p3c5,IoHandler.IO_MB);
        //}
        //}
    }

    
}
